The present invention relates generally to circuitry and protocols associated with operating memory devices, and more particularly to apparatus for controlling multibank memory devices.
FIG. 1 is a simplified functional block diagram of a memory device 200 that represents any of a wide variety of currently available multibank memory devices. The central memory storage unit is a memory array 202 that is arranged in a plurality of banks, with two such banks 204A and 204B shown. The memory array 202 includes a plurality of individual memory elements (not shown) for storing data, with the memory elements commonly arranged in separately addressable rows and columns, as is well known. Those skilled in the art commonly refer to a collectively addressable subset of the array 202 as a xe2x80x9cpage.xe2x80x9d Typically, a single row of memory elements in a bank of the array constitutes a particular page. In FIG. 1, a plurality of pages 206A and 206B are depicted, corresponding with banks 204A and 204B, respectively.
Particular locations within the memory array 202 are addressable by Address signals that external circuitry such as a memory controller (not shown) provides to the memory device 200. The memory controller also provides a plurality of Control or command signals that are used to designate the particular memory access type and/or sequence of memory accesses. As depicted in FIG. 1, a control/address logic circuit 208 receives the Control and Address signals, which may be provided in parallel signal paths, serially, or some suitable combination. The control/address logic circuit 208 then applies a plurality of internal control signals to control the timing and sequence of operations accessing the banks 204A and 204B via access circuits 210A and 210B, respectively. Those skilled in the art will understand that the depicted access circuits 210A and 210B represent a collection of various fictional circuit components commonly found in memory devices. Examples include row and column address latch, buffer, and decoder circuits, sense amplifiers and I/O gating circuitry, and other well-known circuits adapted for particular memory device implementations.
Data written to and read from the memory array 202 is transferred from and to the memory controller or other external circuitry via a data I/O circuit 212 and the access circuits 210A and 210B. Those skilled in the art will also understand that the depicted data I/O circuit 212 represents a collection of various functional circuit components adapted to transmit data to or receive data from external circuitry and to correspondingly receive read data from or transmit write data to the array 202 via the access circuits 210A and 210B.
The memory device 200 depicted in FIG. 1 exemplifies multibank memories such as synchronous dynamic random access memories (SDRAMs) and packet-oriented or synchronous-link DRAMs (known as SLDRAMs). SDRAMs, commonly have two array banks, and SLDRAMs commonly have eight array banks. Providing multiple banks improves the average speed with which a sequence of memory operations can be performed. When access to a particular array bank is complete, a xe2x80x9cprechargexe2x80x9d operation is performed to prepare the corresponding access circuitry for a subsequent data transfer operation with the array bank. The precharge operation requires a certain amount of time for its completion, and therefore limits the speed with which a sequence of memory operations can be performed to a particular array bank. By organizing the memory array to have multiple banks with associated access circuits, the precharge time can, in some instances, be xe2x80x9chidden.xe2x80x9d For example, if a first access is to bank 204A and a subsequent access is to bank 204B, precharge operations associated with bank 204A can occur while executing memory access operations to bank 204B.
Successive memory access operations directed to a single bank ordinarily result in precharge time intervals during which memory access operations cannot be performed. However, if operations are directed to the same page in a given bank (a xe2x80x9cpage hitxe2x80x9d), the successive operations can be performed without precharge. Thus, improving data transfer speed requires detecting the existence of such page hits and interleaving multiple bank and page lit access operations to the memory device 200.
In accordance with the invention, a memory controller is provided for controlling operations of a multibank memory. The memory controller includes a request queue coupled with a control state machine. The request queue stores data transfer requests, and the control state machine receives these requests at respective times and applies control signals to the memory to initiate corresponding data transfer operations. An address detector is coupled with the request queue to determine if a first and second of the data transfer requests constitute a page hit. A hit register is coupled with the address detector and with the request queue and stores the second data transfer request if a page hit. A control timing chain is coupled with the request queue, with the control state machine, and with the hit register. The control timing chain asserts a timing control signal to enable the control state machine to receive the first, second, and a third of the data transfer requests at respective first, second, and third times, with the third time being after the first time and prior to the second time.
In one aspect of the invention, the control timing chain includes a rank register queue through which bank addresses of the data transfer requests propagates. The rank register queue has separate bank access and page access inputs. The bank access input receives the bank addresses of requests for new bank accesses, such as the first and third data transfer requests. The page access input receives the bank address of requests for page hit accesses, such as the second data transfer request from the hit register. Comparator circuitry may be provided to determine the timing of requests being received at the control state machine, as well as to control the timing of bank addresses being received by the rank request queue.
In another aspect of the invention, a computer system is provided that includes a memory controller coupling a processor with a multibank memory. The memory controller is able to initiate a first data transfer request directed to a first bank, to temporarily store a second data transfer request directed to the first bank, and to initiate a third data transfer request directed to a second of the banks prior to initiation of the second data transfer request.